Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask used in manufacture may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target exposure field (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target exposure fields that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target exposure field is irradiated by exposing the entire mask pattern onto the target exposure field in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus—commonly referred to as a step-and-scan apparatus—each target exposure field is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
For the sake of simplicity, the projection system may hereinafter be referred to as the “lens;” however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens”. Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple-stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or the smallest space between two lines. Thus, the CD determines the overall size and density of the designed circuit.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). However, because of the increasingly microscopic size of lithographic features and high resolution systems, the resulting features printed on the substrate tend to have some rippling, i.e., edges that are supposed to be straight are not straight. This rippling is related to “ringing” in filter theory, and is a natural side effect of efforts to accentuate the high spatial frequencies needed to image small features. Others factors that may cause rippling are known by those of ordinary skill in the art. FIG. 1 illustrates features printed on a substrate suffering from the problem of rippling.
In the current state of the art, model-based OPC corrects for mismatch between a target image and predicted image using the following steps. (1) A target layer is divided into a plurality of sections. (2) A predicted image is evaluated at one “evaluation point” (typically at the center) of each section of the plurality of sections. (3) Based on respective evaluations, features to be printed are modified in accordance with the respective evaluation at the center of the corresponding section to minimize the mismatch between the target and predicted image. In low k1 systems with the occurrence of rippling, or in systems where rippling is more prevalent, the conventional model based OPC methods accentuate rippling, as shown generally by FIG. 1, in cases where the evaluation points happen by chance not to be placed in ideally representative locations within their respective sections.
More particularly, FIG. 2 illustrates a target image 20 superimposed on a predicted image 22, which has rippling. The target image 20 is divided into a plurality of sections 24, and the images 22, 24 are evaluated at evaluation points 26 for each section 24. Each evaluation point 26 is located at the center of the respective section 24. Based on these evaluations, the target image is modified (modified mask 30), as illustrated by FIG. 3. The modified mask takes into account the mismatch between the target image 20 and predicted image 22. With respect to the evaluation at the center of each of the plurality of sections 24, an offset of Δn is applied to the target image 20, where n represents the corresponding section 24. In other words, the resulting new edge is adjusted downwardly in each place where the original predication was high, and is adjusted upwardly in each place where the original prediction was low, as would be expected.
FIG. 4 illustrates the new predicted image 40 based on the modified mask 30. By comparison with the predicted image 22, in the given example conventional model based OPC accentuates rippling of the new predicted image 40, which increases the likelihood of breaking or bridging depending on surrounding structure.
Improved results can in principle be obtained by choosing a “better” evaluation point, and some limited strategies exist in this regard. In particular, the evaluation points of sections at or near corners may be moved back away from that corner to avoid over-correction. These methods are helpful, but are difficult to apply except in simple cases due to the complexity of the interaction between surrounding contextual features and the ripples observed on a particular edge of interest.
Moreover, model based OPC uses either an aerial model or a calibrated model. A calibrated model must consider mask properties, characteristics of the tools to create the mask, resist properties, etc. Because of this, there are many disadvantages to using a calibrated model. They include extensive calibration, including building a mask and exposing wafers, and factoring in arbitrary imaging properties that cannot be attributed to the mask, semiconductor, or any associated property. The main disadvantage is that in order to calibrate a model, a reasonable mask must already exist. Thus, industry often uses the aerial model for model based OPC, because it is expedient and does not rely on existing tools. However, aerial models do not factor in product and manufacturing imperfections, as in the case of using a calibrated model.
There has yet to be created a way for eliminating mismatch between a target image and predicted image to approximate real life imperfections.